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ZXFV4089
VIDEO AMPLIFIER WITH DC RESTORATION
DEVICE DESCRIPTION
The ZXFV4089 is a DC restored video amplifier (black-level clamp) in an 8pin SOIC package. It integrates a high performance video amplifier with a nulling sample and hold amplifier specially designed to provide brightness level stability. The input video signal is AC coupled to the main amplifier and this AC coupling capacitor also acts as the holding capacitor for the sample and hold amplifier. This configuration reduces both pin count and external components over traditional solutions. Typically, during the back-porch interval of an analog video waveform the sample and hold amplifier forces the input of the video amplifier to the reference voltage. The video waveform is now referenced to the new reference voltage for the remainder of the line-scan interval. The video amplifier has been optimised for video applications and as such drives back-terminated 75 loads with good differential gain and phase errors. The current feedback architecture allows the bandwidth to remain fixed over a wide range of gains, and is set by two external resistors. The ZXFV4089 is specified for operation at 5V and over the -40C to +85C temperature range and is pin compatible with the industry standard EL4089.
FEATURES AND BENEFITS
* Complete analog video dc level restoration system * Supports various TV systems * PAL, NTSC, SECAM * Excellent video performance * 0.08% differential gain * 0.1 differential phase * 30 MHz 0.1 dB bandwidth * 210 MHz -3 dB bandwidth * 400V/ s slewrate * TTL/CMOS logic compatible HOLD input * Pin and function compatible with industry
standard EL4089
APPLICATIONS
* Black Level Clamp, providing stable intensity in
video systems such as: * cameras
ORDERING INFORMATION
Part Number ZXFV4089N8TA ZXFV4089N8TC Container Reel 7" Reel 13" Increment 500 2500 Part mark ZXFV4089 ZXFV4089
* image capture * video mixing * displays * DC restoration of other high frequency signals
CONNECTION DIAGRAM
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ABSOLUTE MAXIMUM RATINGS - Over operating free-air temperature (unless otherwise stated)1
Positive supply voltage VCC to GND Negative supply Voltage VEE to GND Input voltage, pins 1,2,3 to GND Differential Input Voltage2, pin 1 to pin 2 Output current, pin 7 (continuous, TJ < 110C) Internal power dissipation Input current, IN- pin 1 Current into IN+ and HOLD, pins 2 and 4 Operating ambient temperature range Storage temperature range Operating junction temperature TJMAX -0.5V to +5.5V -5.5V to +0.5V VEE -0.5V to VCC +0.5V 3 V 60 mA See note 3 5 mA 5 mA -40C to 85C -65C to 150C 150C
Notes: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. At high closed loop gains and low gain setting resistors care must be taken if large input signals are applied to the device which cause the output stage to saturate for extended periods of time. 3. The power dissipation of the device when loaded must be designed to keep the device junction temperature below TJMAX, de-rated according to the Theta-ja for the SO8 package, which is typically 168C/W, i.e. 0.74W at 25C. * During power-up and power-down, these voltage ratings require that signals be applied only when the power supply is connected. This device is sensitive to static discharge and proper handling precautions are required.
ESD:
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ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = -5V, G =1, RF = 1k , RLOAD=1k , Tamb = 25C unless otherwise stated.
PARAMETER I CCH I CCS I EEH I EES Positive supply current, holding Positive supply current, sampling Negative supply current, holding Negative supply current, sampling CONDITIONS HOLD = HIGH HOLD = LOW HOLD = HIGH HOLD = LOW MIN 5 5 5 5 TYP 8 8.5 8 8.5 MAX UNIT 10 11 10 11 mA mA mA mA
Amplifier section, Hold Input = High unless otherwise stated V OS I B+ I BR OL R IN+ VO IO +PSRR -PSRR V CMR CMRR Input offset voltage + input bias current - input bias current Trans-impedance + input resistance Output voltage swing Output drive current Positive power supply rejection ratio Negative power supply rejection ratio Common mode input voltage range Common mode rejection ratio
(1)
1 V IN+ = 0V 1 1 V IN+ = 3V 1 VIN+ = 3V,IOUT = 40mA 2.95 40 V CC = 5V5%, V EE = -5V V CC = 5V, V EE = -5V 5% 49 51 3 V IN = 3V 48 57 57 58 1800 2 3.0
10 5 10
mV A A k M V mA dB dB V dB
Restore section, HOLD = Low unless otherwise stated
V OSCOMP
Composite input offset voltage, from VREF V REF = 0V to amplifier output V REF input bias current Input restore current available, pin 2 V REF input voltage range V REF = 0V 180 2 V REF = 2V V CC = 5V5%, V EE = -5V V CC = 5V, V EE = -5V 5% 54 50 50 2
0.3 3 300
7 12 600
mV A A V
I REF I OUT
CMRR +PSRR -PSRR V Hmin V Lmax I IL I IH
NOTES:
Common mode rejection ratio Positive power supply rejection ratio Negative power supply rejection ratio HOLD pin high logic level HOLD pin low logic level Logic low input current Logic high input current
90 60 60
dB dB dB V 0.8 V A A
HOLD = LOW HOLD = HIGH
40 12
100
1. The voltage at the input to pin 2 should be limited to +2.7V for the best DC restoration accuracy. See later explanation under "Common-mode input range."
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AC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = -5V, RF = 470 , G = 2, RLOAD = 150 , CLOAD = 10 pF, TAMB = 25C unless otherwise stated.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Amplifier section HOLD = high unless otherwise stated SR BW -3 BW -3 BW 0.1 dG dP Slew Rate Bandwidth, -3dB Bandwidth, -3dB Bandwidth, 0.1dB Differential gain, NTSC Differential phase, NTSC V OUT = 2V PP V OUT = 0.2V PP , G = 2 V OUT = 0.2V PP , G = 1, R f = 820 V OUT = 0.2V PP f = 3.58 MHz, V IN = 280mV pk-pk, DC = -714 to +714 mV 400 210 210 30 0.08 0.1 V/s MHz MHz MHz % deg
Restore section HOLD = low unless otherwise stated SR t ENH t DISH Slew rate Time to enable hold Time to disable hold V OUT = 2V PP , C HOLD = 0.01F* 25 25 40 V/s ns ns
* Slew rate is dependent on the ac coupling hold capacitor connected to pin 2.
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TYPICAL CHARACTERISTICS
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TYPICAL CHARACTERISTICS (CONT.)
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ZXFV4089 DETAILED OPERATING NOTES
Introduction This device provides an uncommitted video feed-back amplifier together with a sample-hold system to allow restoration or level-shifting of the input waveform to a controlled DC level. The Connection Diagram, Figure 1 (page 1) shows a typical video signal application. No output termination is shown in the diagram, but if desired the output can drive a 75 cable via a 75 series terminating resistor. Amplifier configuration The main amplifier uses current feedback in a non-inverting configuration. Two external resistors are required to set the gain. An external reference, VREF, normally ground, is used to set the new DC level of the video signal. The input video signal is applied via an external input AC coupling capacitor, which is used to store a DC control level when the sample-hold switch is open. Typically an external sampling pulse (active low) is applied to the HOLD input. During this pulse, the sample-hold switch is closed. This completes the DC feedback loop and the stored level is driven towards a new value. At the end of the sampling pulse, the switch opens again and the DC level remains close to the new established value until the next sample pulse. The sample-hold charging current is limited to 300 A. Therefore the convergence towards the steady condition is typically slow, but after several HOLD pulse cycles, the DC level settles closely to the Reference level at the VREF input. The sample-hold loop contains the video amplifier within its path, and also includes an additional sample-hold sense amplifier that compares VREF with the output voltage using an internal low-pass filter. In the high state, the switch is open and the average DC level remains fixed apart from a small drift due to the input bias current of the amplifier and switch leakage (see below). DC restoration The HOLD input is a TTL compatible signal that is buffered and controls the sample-hold switch. A logic LOW state closes the switch and so enables the feedback control loop to set the output level equal to V REF (usually ground). The level of DC shift is maintained when the logic control returns to the HIGH state and the switch opens. In this way the whole waveform is conditionally level shifted, or 'restored' to the new DC level. Figure 2 shows the response of the circuit to a stationary or very slowly varying waveform with an initial voltage offset difference between V+ and VREF, applied to the input coupling capacitor, when the HOLD input is cycled with a repetitive pulse waveform. When the HOLD input is at a logic LOW level, the signal input V+ is driven towards VREF. After a number of cycles, the waveform settles to the DC stabilised value. The waveform is unaffected during the logic HIGH interval of the HOLD input. Figure 2: RESPONSE TO SLOW INPUT SIGNAL Figure 3 shows a portion of a typical video waveform, where the sample pulse is synchronised to fall within the back porch interval. This can for example be achieved using the Zetex ZXFV4583 Sync Separator to derive the pulse as in the Evaluation Circuit described in the data sheet for that part. Again, during the logic LOW period of the HOLD input, the waveform is driven towards VREF. Eventually, after a few line scans, the video waveform is stabilised with the back porch level equal to VREF and this condition is maintained despite any small changes in the input waveform.
Figure 3: RESPONSE TO TYPICAL VIDEO SIGNAL In the video application, the HOLD input state will be HIGH during the picture line sweep and a negative-going sampling pulse of typically 1.2 s duration will be applied during a central portion of the Back Porch interval, so that the Back Porch or 'Black' level is clamped to VREF (typically ground). If desired, by changing the external pulse timing the signal may be restored such that the sync tip voltage is clamped to VREF instead of the back porch. In either case, for each line scan, this gives a brightness level consistent with that of the original camera signal, despite the AC coupling. The value of the coupling capacitor affects two main characteristics of the circuit: 1. DC level acquisition change 2. DC Level droop
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DC Level Acquisition change In the restore mode the available charging current, together with the capacitor value, determines the maximum DC voltage correction which can be applied at each sample. For a charging current limit of 300 A applied for 1.2 s, the charge injected is: Qmax = 300 A x 1.2 s = 360 pC Then the maximum voltage shift correction is: Vmax = Qmax/C = 360 pC / 0.01 F = 36 mV DC Level Droop In the hold state, a small voltage drift is caused by leakage from the Sample-hold circuit and bias current from the main amplifier charging or discharging the coupling capacitor. The drift rate is equal to the bias/leakage current of up to about 1 A divided by the coupling capacitor value. For a coupling capacitor of 0.01 F the drift rate is then up to 100 V/s. For a typical video line scan the switch remains open for the rest of the scan duration, or about 62 s. The drift at the end of the line scan has therefore accumulated to about 6.2 mV. This is acceptable for most applications, but if desired it can be reduced by increasing the value of the coupling capacitor. This will result in a proportionately smaller value of the maximum available correction voltage at each scan as described above. Normally, once settled, the video system requires only a very small correction at each scan, so this will not present any problem. Supply filtering & printed circuit layout In the applied circuit, the power filtering and printed layout design needs special attention as is appropriate for a high-speed analog circuit. For each supply lead, use a leadless ceramic chip capacitor placed very close to the device power pin. A value of 0.1F is recommended. In addition, a larger value capacitor, which should be ceram ic or solid tantalum construction, with a value of 1 to 10 F, is also recommended for connection to each supply fairly close to the device. The layout naturally requires some short interconnections on the component side (top copper layer) and a continuous ground plane should be provided on another layer with plated via holes providing low inductance ground connections for the device and other components. The amplifier frequency response is affected to some extent by stray capacitance at the inverting input at pin 1. This effect can be minimised by providing a small cut-out area in the ground plane and other layers around pin 1, though this may not always be necessary for the application. Further Applications Information The ZXFV4089 is a high speed device requiring the appropriate care in the layout of the application printed circuit board. A continuous ground plane construction is preferred. Suitable power supply decoupling suggested includes a 100nF leadless ceramic capacitor close to the power supply connections at pin 8 and pin 6. As stated earlier the main video amplifier of the ZXFV4089 is a current feedback amplifier. Compared to a voltage-feedback amplifier, current feedback provides better bandwidths at higher gains and also much faster slew rates. To optimise performance from a current feedback amplifier choice of feedback resistor is very important. In this case, typically the device will be used with a voltage gain of two, using two resistors of 1k as in Figure 1. Stray capacitance at the inverting input node of this circuit can affect frequency and pulse response, so the printed circuit layout should take account of this. Place the feedback resistors as close as possible to the inverting input pin and minimise the printed metal connected to this pin. Common-mode input range The signal input voltage range is determined partly by the common-mode input range of the main amplifier. The amplifier configuration is non-inverting, and so the inverting input will follow the signal input voltage. It is also necessary to observe the maximum limit on the value of VREF (2V) which is less than the amplifier input voltage range. Therefore the input range of the system is limited to this value. In addition the restore amplifier voltage input range is restricted to a similar value. Attention is drawn to the footnote of the DC Electrical Characteristics Table, regarding input signal amplitude. The video signal is ac coupled into the main amplifier and clamped to VREF. As a result of this the actual voltage seen by the device input at pin 2 is the sum of VREF plus the video input signal voltage excursion above VREF (when clamping the back porch, this excursion is normally the luminance waveform of up to about 0.72V white level). At a particular positive value at pin 2 close to 2.7V, the leakage current of the Sample-hold switch increases causing an increase in the droop rate. Therefore, for example, a reference voltage of 2V with a peak white video signal of 0.7V could result in increased restoration error arising from the increased DC offset. If pin 2 is driven above +2.7V peak voltage the DC restoration accuracy could be affected and care should be taken in this respect. When using 0.7V luminance, this is consistent with the maximum recommended reference voltage of +2V. Evaluation Circuit An evaluation circuit is available to allow demonstration of the video black-level clamping function. The circuit uses the Zetex ZXFV4583 Sync Separator circuit to provide the HOLD function timing signal. This circuit is described in the data sheet for ZXFV4583. To order the evaluation board, ask for ZXFV4583EV. ISSUE 2 - SEPTEMBER 2005
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PACKAGE OUTLINE
Controlling dimensions are in millimeters. Approximate conversions are given in inches
PACKAGE DIMENSIONS
Millimeters DIM Min A A1 D H E L 0.053 0.004 0.189 0.228 0.150 0.016 Max 0.069 0.010 0.197 0.244 0.157 0.050 Min 1.35 0.10 4.80 5.80 3.80 0.40 Max 1.75 0.25 5.00 6.20 4.00 1.27 h e b c Inches DIM Min Max Min Max 0.050 BSC 0.013 0.008 0 0.010 0.020 0.010 8 0.020 1.27 BSC 0.33 0.19 0 0.25 0.51 0.25 8 0.50 Millimeters Inches
(c) Zetex Semiconductors plc 2005
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